reservation
posted 13d ago↗ original on DOU
> DOU + DJINNI
FPGA Engineer — вакансії в Україні
Усі відкриті вакансії FPGA Engineer з DOU і Djinni — 23 вакансії в одному списку. Повторні публікації однієї вакансії згорнуті в одну картку, тому той самий оффер не трапиться двічі.
Відкрити у фіді з фільтрами →posted 17d ago↗ original on Djinni
officeKyiv, Ukraine
2+ years
rtosfpgalabviewdigital signal processingmatlabembedded cvivadoverilogsimulinklinux
hilaltium designersil
reservation
posted 22d ago↗ original on DOU
contract
senior
FPGA Engineer
5+ years
lvdsfpgasystemveriloglogic analyzerverilogoscilloscopemipi csi
cuavsensorsxilinxpython
posted 27d ago↗ original on Djinni
Kyiv, Ukraine
senior
FPGA Engineer
2+ years
dmai2cgpiospiethernetuartsystemverilogvivadoverilogaxiuvm
lvdsembedded linuxcc++mipi csi
reservation
posted 28d ago↗ original on DOU
officeKyiv, Ukraine
2+ years
rtosmatlabembedded cpcievivadoverilogsimulinkyocto
altium designer
reservation
posted 29d ago↗ original on DOU
posted 2026-09-03 08:36:57 UTC↗ original on Djinni
reservation
posted 2026-08-11 13:41:18 UTC↗ original on Djinni
reservation
posted 2026-08-06 09:41:02 UTC↗ original on Djinni
posted 2026-08-06 06:37:45 UTC↗ original on Djinni
officefull-timeBerlin, Germany
senior
FPGA Engineer
C1–C2
7.5k–10k EURdmasdrradardspfpgahardware testingsystemverilogc++embedded cpcievivadoverilogaxi
lvdsembedded linuxyocto
posted 2026-08-03 07:28:24 UTC↗ original on Djinni
dmadspfpgartlsystemverilogvivadoverilogaxi
matlabcc++python
posted 2026-07-31 10:36:50 UTC↗ original on Djinni
posted 2026-07-28 07:32:43 UTC↗ original on DOU
reservation
posted 2026-07-24 09:37:16 UTC↗ original on Djinni
officeKyiv, Ukraine
senior
FPGA Engineer
2+ years
dspfpgasystemverilogverilog
numpyethernetembedded linuxbuildrootmatlab
reservation
posted 2026-07-20 07:03:26 UTC↗ original on DOU
reservation
posted 2026-07-13 11:15:24 UTC↗ original on Djinni
officeKyiv, Ukraine
lvdsdspquartusethernetsystemverilogpcievivadoverilogxilinx
rtososcilloscopesoc
reservation
posted 2026-07-10 11:18:59 UTC↗ original on Djinni
Kyiv, Ukraine
middle
FPGA Engineer
2+ years
fpgasystemverilogverilog
sdrembedded linuxbuildrootmatlabpcie
reservation
posted 2026-06-22 06:44:05 UTC↗ original on DOU
officeKyiv, Ukraine
lvdsfpgaethernetdigital signal processingsystemverilogpcieverilogarm
i2cspiuartrisc-v
reservation
posted 2026-06-16 12:25:56 UTC↗ original on DOU
officefull-timeKyiv, Ukraine
junior
FPGA Engineer
1+ years
quartusfpgaclogic analyzerc++vivadoverilogoscilloscopepython
dspxilinx zynqci/cdsoc
reservation
posted 2026-06-09 09:09:13 UTC↗ original on Djinni