> Djinni
senior
Hardware Engineer
jtagperltclshell scripting
python
> full description
Must-Have Requirements
- BSc in Electrical Engineering from a recognized university.
- Minimum 3 years of hands-on DFT experience — must. Senior-level profiles preferred.
- DFT methodologies: scan, ATPG, at-speed test, memory BIST, I/O DFT.
- Scan insertion and ATPG for stuck-at, transition-delay, bridging and IDDQ fault models; test-coverage improvement.
- DFT DRC analysis and coverage debug with Synopsys DFT Compiler / TestMAX (TetraMAX) / SpyGlass DFT or equivalent Siemens (Mentor) Tessent tools.
- Memory BIST — Tessent MBIST.
- Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6 and IEEE 1500 (formerly P1500).
- Hands-on design and implementation of DFT features.
- End-to-end DFT flow ownership: concept → tape-out → production.
- Gate-level simulation setup and runs (pattern validation).
- Formal equivalence checking.
- Perl / Tcl / UNIX scripting for flow automation.
Nice to Have
- Broader Siemens Tessent experience (ScanPro / TestKompress, LBIST) beyond MBIST.
- Advanced-node experience (7nm and below).
- Python for flow automation.